June 11, 2015 – Aitech Defense Systems Inc., has expanded the on-board memory of its SP0, a space-qualified 3U SBC (single board computer) that has been fully tested and characterized at the NASA-approved UC Davis proton and Texas A&M heavy ion cyclotrons.
Conduction-cooled with from 1 to 8 GB of user Flash, the enhanced 3U CompactPCI SBC can easily handle additional processes and user data storage to provide the critical functionality needed in the harsh, remote environment of space. The low overall power consumption of only 10 W is ideal for high performance, in-orbit systems.
The SP0 is fully qualified and radiation characterized to over 100 kRad (Si) and is latch-up immune to greater than 37 MeV-cm2/mg to reliably operate in LEO (low) and MEO (medium) orbits as well as show a high confidence for use in GEO (geostationary) orbits.
In addition to the 8 GB of ECC (error check and correct) user NAND Flash, the board offers up to 512 MB of fast DDR SDRAM, also with ECC protection, for high data integrity. The 512 KB of redundant Boot EEPROM provides high confidence in the proper execution of the initial boot sequence with auto-failover as needed to meet both processor and application needs.
The board uses the radiation-tolerant Freescale Silicon-on-Insulator (SOI) MPC8548E PowerQUICC-III 1.17 GHz processor that provides 333.3 MHz of core complex bus (CCB) and an e500 System-on-Chip (SoC). The SoC integrates both an on-chip 32 KB instruction and 32 KB data L1 cache as well as a 512 KB L2 cache.
Algorithms developed by Aitech over many years automatically deal with L1/L2 cache mitigation as well as the characterization, tracking and logging of single event effects and upsets of this, and other on-board, resources.
The board features two Gigabit Ethernet ports, four asynchronous, high-speed serial communications ports and up to five general purpose discrete I/O channels. A 1 pps (pulse per second) input port is provided to allow the time synchronization of multiple compute elements in the platform.
All I/O are routed to the rear panel connectors to simplify system integration. This extensive on-board I/O potentially reduces the number of additional peripheral cards needed to implement a fully functional subsystem.
An industry-standard PMC slot as well as up to eight PCI Express lanes and dual PCI buses add even more on-board functionality and performance to the SP0.
Built for exceptional safety and reliability, the board features three watchdog timers. The first, located within the SoC processor, generates an internal CPU interrupt to alert the application of a pending fault. The second, external to the processor, can reset the whole board after the first expiration period.
After the first and second timers expire, a non-maskable hardware reset is performed and resets the entire board. Housed in the on-board FPGA, the third timer can reset the whole board or only certain I/O devices after the expiration period.
Tested to 100 kRad (Si) TID; latch-up immune to 37 MeV-cm2/mg
PowerPC MPC8548E PowerQUICC-III processor
e500 SoC with 32 KB instruction/32 KB data L1 cache and 512 KB L2 cache
Low power: 10 W consumption
Unlimited design flexibility with extensive I/O interfaces
Multiple configurations and components for lab development, engineering prototype and flight units to meet various budget requirements
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